clk /en mr function z l l divide zz h l hold q 0? x x h reset q 0? the SY100S839V is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the device can be driven by either a differential or single-ended ecl/lvecl or, if positive power supplies are used, pecl/lvpecl input signal. in addition, by using the v bb output, a sinusoidal source can be ac-coupled into the device. if a single- ended input is to be used, the v bb output should be connected to the /clk input and bypassed to ground via a 0.01 f capacitor. the v bb output is designed to act as the switching reference for the input of the s839v under single-ended input conditions. as a result, this pin can only source/sink up to 0.5ma of current. the common enable (/en) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. upon start-up, the internal flip-flops will attain a random state; the master reset (mr) input must be asserted to ensure synchronization. for systems which only use one s839v, the mr pin need not be exercised as the internal divider designs ensures synchronization between the 2/4, and the 4/5/6 outputs of a single device. pin configuration/block diagram 3.3v and 5v power supply option 50ps output-to-output skew 50% duty cycle outputs synchronous enable/disable master reset for synchronization internal 75k ? input pull-down resistors available in 20-pin soic package truth table description features rev.: a amendment: /0 issue date: may, 1999 2/4, 4/5/6 clock generation chip note: z = low-to-high transition zz = high-to-low transition clockworks SY100S839V final pin function clk differential clock inputs /en synchronous enable mr master reset v bb reference output q 0, q 1 differential 2/4 outputs q 2, q 3 differential 4/5/6 outputs divsel frequency select input pin names divselb1 divselb0 q 2, q 3 outputs 0 0 divide by 4 0 1 divide by 6 1 0 divide by 5 1 1 divide by 5 divsela q 0, q 1 outputs 0 divide by 2 1 divide by 4 v cc q 0 q 0 q 1 q 1 q 2 q 2 q 3 q 3 v ee v cc en divselb0 clk clk v bb mr v cc 12345678910 20 19 18 17 16 15 14 13 12 11 top view soic z20-1 divselb1 divsela 1
2 clockworks SY100S839V micrel t a = 40 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i ee power supply current 50 95 50 95 50 95 54 95 ma v bb output reference 1.38 1.26 1.38 1.26 1.38 1.26 1.38 1.26 v voltage i ih input high current 150 150 150 150 a v oh output high voltage (2) 1085 1005 880 1025 955 880 1025 955 880 1025 955 880 mv v ol output low voltage (2) 1830 1695 1555 1810 1705 1620 1810 1705 1620 1810 1705 1620 mv v oha output high voltage (3) 1095 1035 1035 1035 mv v ola output low voltage (3) 1555 1610 1610 1610 mv v ih input high voltage 1165 880 1165 880 1165 880 1165 880 mv v il input low voltage 1810 1475 1810 1475 1810 1475 1810 1475 mv i il input low current (4) 0.5 0.5 0.5 0.5 a dc electrical characteristics (1) v ee = v ee (min) to v ee (max); v cc = gnd note: 1. parametric values specified at: -3.0v to -3.8v or -4.2v to -5.5v. 2. v in = v ih (max) or v il (min): loading with 50 ? to 2.0v. 3. v in = v ih (min) or v il (max): loading with 50 ? to 2.0v. 4. v in = v il (min) .
3 clockworks SY100S839V micrel t a = 40 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit f max maximum toggle frequency 1000 1000 1000 1000 mhz t plh propagation delay to output ps t phl clk ? output (diff.) 725 925 725 925 725 925 725 925 clk ? output (s.e.) 675 975 675 975 675 975 675 975 mr ? output 600 900 600 900 610 910 630 930 t skew within-device skew (2) q 0 q 3 50 50 50 50 ps part-to-part q 0 q 3 (diff.) 200 200 200 200 t s set-up time /en ? /clk 250 250 250 250 ps divsel ? clk 400 400 400 400 t h hold time /clk ? /en 100 100 100 100 ps clk ? divsel 150 150 150 150 v pp minimum input swing (3) clk 250 250 250 250 mv v cmr common mode range (4), (5) -1.6 -0.4 -1.7 -0.4 -1.7 -0.4 -1.7 -0.4 v t rr reset recovery time 100 100 100 100 ps t pw minimum pulse width clk 500 500 500 500 ps mr 700 700 700 700 tr output rise/fall times q 280 550 280 550 280 550 280 550 ps t f (20% 80%) ac electrical characteristics (1) v ee = v ee (min) to v ee (max); v cc = gnd notes: 1. parametric values specified at: -3.0v to -3.8v or -4.2v to -5.5v. 2. skew is measured between outputs under identical transitions. 3. minimum input swing for which ac parameters are guaranteed. the device will function reliably with differential inputs down to 100mv. 4. the cmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min. and 1v. the lower end of the cmr range varies 1:1 with v ee . the numbers in the spec table assume a nominal v ee = 3.3v. note for pecl operation, the v cmr (min) will be fixed at 3.3v iv cmr (min)i. 5. duty cycle: (min. 48%; max. 52%) } over temp.
4 clockworks SY100S839V micrel logic diagram timing diagrams product ordering code ordering package operating code type range SY100S839Vzc z20-1 commercial SY100S839Vzctr z20-1 commercial clk clk en mr divselb0 q 0 r r q 0 q 1 q 1 q 2 q 2 q 3 q 3 ( 2/4) ( 4/5/6) divsela divselb1 v bb clk q ( 2) q ( 4) q ( 5) q ( 6)
5 clockworks SY100S839V micrel 20 lead soic .300" wide (z20-1) rev. 03 micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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